1. Field of the Invention
This invention relates to a fabrication method of a semiconductor device such as a Bi-CMOS-SRAM or the like.
2. Description of the Related Art
A larger capacity, higher speed SRAM (Static Random Access Memory) has been required recently, under such a circumstance, a Bi-CMOS (Bipolar-Complementary Metal Oxide Semiconductor) -SRAM has been attracting strong attention in that it can be provided with both larger capacity and higher speed properties.
In general, as the integration of memory cells of an SRAM is progressed, the capacity of a storage node becomes small, resulting in a reduction in alpha-ray resistivity, which means an increase in possibility of a "soft error". If an alpha-ray is incident to the source and drain regions of the storage node, it penetrates up to a depth of about 30 .mu.m to generate electron-hole pairs along its locus. The electric charges thus generated are drifted and diffused to be absorbed into the storage node thereby causing the data stored in the storage cells to be destroyed.
To restrain the soft error, conventionally, such a structure that an N.sup.- -buried layer is provided between a silicon substrate and an epitaxial layer grown on the substrate has been employed. A conventional fabrication method of a Bi-CMOS-SRAM having the structure will be explained below by referring to FIG. 1, which shows only an N-channel MOSFET of a memory cell thereof.
First, a P-silicon substrate 31 is selectively applied with an ion-implantation of phosphorus at a dose of 1.times.10.sup.13 to 5.times.10.sup.13 cm.sup.-2 and annealed at a temperature as high as 1200.degree. C. to form an N.sup.- -buried layer 32 therein. Then, the buried layer 32 is selectively applied on its surface with an ion-implantation of boron at a dose of 5.times.10.sup.13 to 1.times.10.sup.14 cm.sup.12 to obtain a P.sup.+ -buried buried layer 33. Here, the thickness of the N.sup.- -buried layer 32 between the P-silicon substrate 31 and the P.sup.+ -buried layer 33 is generally about 4 to 5 .mu.m. And thereafter, an ion-implantation of arsenic is selectively applied to the periphery of the N.sup.- -buried layer 32 to form an N.sup.+ -buried layer 34 which acts as an isolation layer.
Next, an N-epitaxial layer 35 is grown on the surfaces of the P-buried layer 33 and the N.sup.+ -buried layer 34 and the exposed surfaces of the N.sup.- -buried layer 32. Then, a P-well 36 is formed in the epitaxial layer 35 so as to attain the P-buried layer 33. On the surface of the epitaxial layer 35 and that of the P-well 36, a field oxide film 37 for isolation use is formed by the LOCOS (Local Oxidation of Silicon) technique. The field oxide film 37 is disposed just above the N.sup.+ -buried layer 34.
Subsequently, a gate oxide film 38 with a thickness of 15 to 20 nm is formed on the P-well 36, and a polysilicon gate electrode 39a is formed on the film 38.
Next, an ion-implantation of phosphorus is applied to the P-well 36 at a dose of 5.times.10.sup.15 cm.sup.2 with the gate electrode 39a and the field oxide film 37 as a mask to form a source region 41 and a drain region 42 of the N-channel MOSFET, which are self-aligned with the gate electrode 39a. The state at this time is shown in FIG. 1.
A wiring layer, an interlayer insulation film and a passivation layer (not shown) are formed on the films 37, 38 and the gate electrode 39a by the known methods. Thus, the Bi-CMOS-SRAM in which the storage node is surrounded by the N-type regions 32 and 34 in the substrate 31 is obtained.
In the SRAM, when alpha-ray is incident to the source and drain regions 41 and 42 of the storage node, the alpha-ray generally penetrates up to a depth of about 30 .mu.m. The electric charges generated by the alpha-ray are absorbed into the lightly-doped N.sup.- -buried layer 32 and as a result, the soft error in the memory cell is difficult to occur, which means that the soft error rate can be reduced.
There has been known the fact that in the ion-implantation and plasma etching processes for fabricating the semiconductor device such as the above-described SRAM, electric charges are generated and remain on the surface of the silicon substrate 31. In the case, since the P-well 36 or the storage node is electrically insulated from the N.sup.- -buried layer 32, the N.sup.+ -buried layer and the N-epitaxial layer 35, the electric charges cannot discharge from the substrate 31 and remain on the surface of the substrate 31. The phenomenon has been called "charge up". As a result, the remaining charges are accumulated on the N.sup.- -buried layer 32 for restraining the soft error thereby to vary the threshold voltage of the N-channel MOSFET, and in the worst possible case, the gate oxide film 38 is damaged typically, arising a problem that causes the various characteristics of the FET to be deteriorated.